AT87251G2D-3CSUM【PDF 32/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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AT/TSC8x251G2D

4135F–8051–11/06

Add 3 if it addresses a Peripheral SFR.

5. If this instruction addresses an I/O Port (Px, x = 0-3), add 3 to the number of states.

Add 5 if it addresses a Peripheral SFR.

6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the des-

tination address is internal and odd.

Table 31.

Summary of Unconditional Jump Instructions

Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

2. In internal execution only, add 1 to the number of states if the destination address is

internal and odd.

3. Add 2 to the number of states if the destination address is external.

4. Add 3 to the number of states if the destination address is external.

Absolute jumpAJMP <src>(PC)

← (PC) +2; (PC)10:0 ← src opnd

Extended jumpEJMP <src>(PC)

← (PC) + size (instr); (PC)23:0 ← src opnd

Long jumpLJMP <src>(PC)

← (PC) + size (instr); (PC)15:0 ← src opnd

Short jumpSJMP rel(PC)

← (PC) +2; (PC) ← (PC) +rel

Jump indirectJMP at A +DPTR(PC)23:16 ← FFh; (PC)15:0 ← (A) + (DPTR)

No operationNOP(PC)

← (PC) +1

Mnemonic

<dest>,

<src>

(1)

Comments

Binary Mode

Source Mode

Bytes

States

Bytes

States

AJMP

addr11

Absolute jump

3(2)(3)

23(2)(3)

EJMP

addr24

Extended jump

6(2)(4)

45(2)(4)

at DRk

Extended jump (indirect)

7(2)(4)

26(2)(4)

LJMP

at WRj

Long jump (indirect)

6(2)(4)

25(2)(4)

addr16

Long jump (direct address)

5(2)(4)

35(2)(4)

SJMP

rel

Short jump (relative address)

4(2)(4)

24(2)(4)

JMP

at A +DPTR

Jump indirect relative to the DPTR

5(2)(4)

15(2)(4)

NOP

No operation (Jump never)

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